/*
 * Copyright (c) 2021-2022 International Innovation Center of Tsinghua University, Shanghai
 * Ventus is licensed under Mulan PSL v2.
 * You can use this software according to the terms and conditions of the Mulan PSL v2.
 * You may obtain a copy of Mulan PSL v2 at:
 *          http://license.coscl.org.cn/MulanPSL2
 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
 * See the Mulan PSL v2 for more details. */
package CTA

import chisel3._

class cta_scheduler(val NUMBER_CU: Int, val CU_ID_WIDTH: Int, val RES_TABLE_ADDR_WIDTH: Int, val VGPR_ID_WIDTH: Int, val NUMBER_VGPR_SLOTS: Int, val SGPR_ID_WIDTH: Int, val NUMBER_SGPR_SLOTS: Int, val LDS_ID_WIDTH: Int, val NUMBER_LDS_SLOTS: Int, val WG_ID_WIDTH: Int, val WF_COUNT_WIDTH: Int, val WG_SLOT_ID_WIDTH: Int, val NUMBER_WF_SLOTS: Int, val WF_COUNT_MAX: Int, val NUMBER_RES_TABLE: Int, val GDS_ID_WIDTH: Int, val GDS_SIZE: Int, val ENTRY_ADDR_WIDTH: Int, val NUMBER_ENTRIES: Int, val WAVE_ITEM_WIDTH: Int, val MEM_ADDR_WIDTH: Int, val TAG_WIDTH: Int, val INIT_MAX_WG_COUNT: Int, val WF_COUNT_WIDTH_PER_WG: Int) extends Module{
    val io = IO(new Bundle{
        val host_wg_valid = Input(Bool())
        val host_wg_id = Input(UInt(WG_ID_WIDTH.W)) // wg_tag_id
        val host_kernel_size_3d = Input(Vec(3, UInt(top.parameters.WG_SIZE_X_WIDTH.W)))
        val host_num_wf = Input(UInt(WF_COUNT_WIDTH_PER_WG.W))
        val host_wf_size = Input(UInt(WAVE_ITEM_WIDTH.W))
        val host_start_pc = Input(UInt(MEM_ADDR_WIDTH.W))
        val host_gds_baseaddr = Input(UInt(MEM_ADDR_WIDTH.W))
        val host_vgpr_size_total = Input(UInt((VGPR_ID_WIDTH + 1).W))
        val host_sgpr_size_total = Input(UInt((SGPR_ID_WIDTH + 1).W))
        val host_lds_size_total = Input(UInt((LDS_ID_WIDTH + 1).W))
        val host_gds_size_total = Input(UInt((GDS_ID_WIDTH + 1).W))
        val host_pds_baseaddr = Input(UInt(MEM_ADDR_WIDTH.W))
        val host_csr_knl = Input(UInt(MEM_ADDR_WIDTH.W))
        val host_vgpr_size_per_wf = Input(UInt((VGPR_ID_WIDTH + 1).W))
        val host_sgpr_size_per_wf = Input(UInt((SGPR_ID_WIDTH + 1).W))
        val inflight_wg_buffer_host_rcvd_ack = Output(Bool())
        val inflight_wg_buffer_host_wf_done = Output(Bool())
        val inflight_wg_buffer_host_wf_done_wg_id = Output(UInt(WG_ID_WIDTH.W))
        val dispatch2cu_wf_dispatch = Output(UInt(NUMBER_CU.W))
        val dispatch2cu_wg_wf_count = Output(UInt(WF_COUNT_WIDTH_PER_WG.W))
        val dispatch2cu_wf_size_dispatch = Output(UInt(WAVE_ITEM_WIDTH.W))
        val dispatch2cu_sgpr_base_dispatch = Output(UInt((SGPR_ID_WIDTH + 1).W))
        val dispatch2cu_vgpr_base_dispatch = Output(UInt((VGPR_ID_WIDTH + 1).W))
        val dispatch2cu_wf_tag_dispatch = Output(UInt(TAG_WIDTH.W))
        val dispatch2cu_lds_base_dispatch = Output(UInt((LDS_ID_WIDTH + 1).W))
        val dispatch2cu_start_pc_dispatch = Output(UInt(MEM_ADDR_WIDTH.W)) // TODO:
        val dispatch2cu_kernel_size_3d_dispatch = Output(Vec(3, UInt(top.parameters.WG_SIZE_X_WIDTH.W)))
        val dispatch2cu_pds_baseaddr_dispatch = Output(UInt(MEM_ADDR_WIDTH.W))
        val dispatch2cu_csr_knl_dispatch = Output(UInt(MEM_ADDR_WIDTH.W))
        val dispatch2cu_gds_base_dispatch = Output(UInt(MEM_ADDR_WIDTH.W))
        val cu2dispatch_wf_done = Input(UInt(NUMBER_CU.W))
        val cu2dispatch_wf_tag_done = Vec(NUMBER_CU, Input(UInt(TAG_WIDTH.W)))
        val cu2dispatch_ready_for_dispatch = Vec(NUMBER_CU, Input(Bool()))
    })
    //Wire to connect all sub-modules
    val dis_controller_wg_alloc_valid = Wire(Bool())
    val dis_controller_start_alloc = Wire(Bool())
    val dis_controller_wg_dealloc_valid = Wire(Bool())
    val dis_controller_wg_rejected_valid = Wire(Bool())
    val allocator_wg_id_out = Wire(UInt(WG_ID_WIDTH.W))
    val gpu_interface_dealloc_wg_id = Wire(UInt(WG_ID_WIDTH.W))
    val inflight_wg_buffer_alloc_valid = Wire(Bool())
    val inflight_wg_buffer_alloc_available = Wire(Bool())
    val inflight_wg_buffer_alloc_wg_id = Wire(UInt(WG_ID_WIDTH.W))
    val inflight_wg_buffer_alloc_num_wf = Wire(UInt(WF_COUNT_WIDTH_PER_WG.W))
    val inflight_wg_buffer_alloc_vgpr_size = Wire(UInt((VGPR_ID_WIDTH + 1).W))
    val inflight_wg_buffer_alloc_sgpr_size = Wire(UInt((SGPR_ID_WIDTH + 1).W))
    val inflight_wg_buffer_alloc_lds_size = Wire(UInt((LDS_ID_WIDTH + 1).W))
    val inflight_wg_buffer_gpu_valid = Wire(Bool())
    val inflight_wg_buffer_gpu_vgpr_size_per_wf = Wire(UInt((VGPR_ID_WIDTH + 1).W))
    val inflight_wg_buffer_gpu_sgpr_size_per_wf = Wire(UInt((SGPR_ID_WIDTH + 1).W))
    val inflight_wg_buffer_gpu_wf_size = Wire(UInt(WAVE_ITEM_WIDTH.W))
    val inflight_wg_buffer_start_pc = Wire(UInt(MEM_ADDR_WIDTH.W))
    val inflight_wg_buffer_kernel_size_3d = Wire(Vec(3, UInt(top.parameters.WG_SIZE_X_WIDTH.W)))
    val inflight_wg_buffer_pds_baseaddr = Wire(UInt(MEM_ADDR_WIDTH.W))
    val inflight_wg_buffer_csr_knl = Wire(UInt(MEM_ADDR_WIDTH.W))
    val inflight_wg_buffer_gds_base_dispatch = Wire(UInt(MEM_ADDR_WIDTH.W))
    val allocator_cu_id_out = Wire(UInt(CU_ID_WIDTH.W))
    val allocator_wf_count = Wire(UInt(WF_COUNT_WIDTH_PER_WG.W))
    val allocator_vgpr_start_out = Wire(UInt(VGPR_ID_WIDTH.W))
    val allocator_sgpr_start_out = Wire(UInt(SGPR_ID_WIDTH.W))
    val allocator_lds_start_out = Wire(UInt(LDS_ID_WIDTH.W))
    val gpu_interface_alloc_available = Wire(Bool())
    val gpu_interface_dealloc_available = Wire(Bool())
    val gpu_interface_cu_id = Wire(UInt(CU_ID_WIDTH.W))
    val grt_cam_up_valid = Wire(Bool())
    val grt_cam_up_wf_count = Wire(UInt(WF_COUNT_WIDTH.W))
    val grt_cam_up_wg_count = Wire(UInt((WG_SLOT_ID_WIDTH + 1).W))
    val grt_cam_up_cu_id = Wire(UInt(CU_ID_WIDTH.W))
    val grt_cam_up_vgpr_strt = Wire(UInt(VGPR_ID_WIDTH.W))
    val grt_cam_up_vgpr_size = Wire(UInt((VGPR_ID_WIDTH + 1).W))
    val grt_cam_up_sgpr_strt = Wire(UInt(SGPR_ID_WIDTH.W))
    val grt_cam_up_sgpr_size = Wire(UInt((SGPR_ID_WIDTH + 1).W))
    val grt_cam_up_lds_strt = Wire(UInt(LDS_ID_WIDTH.W))
    val grt_cam_up_lds_size = Wire(UInt((LDS_ID_WIDTH + 1).W))
    val grt_wg_alloc_done = Wire(Bool())
    val grt_wg_alloc_wg_id = Wire(UInt(WG_ID_WIDTH.W))
    val grt_wg_alloc_cu_id = Wire(UInt(CU_ID_WIDTH.W))
    val grt_wg_dealloc_done = Wire(Bool())
    val grt_wg_dealloc_wg_id = Wire(UInt(WG_ID_WIDTH.W))
    val grt_wg_dealloc_cu_id = Wire(UInt(CU_ID_WIDTH.W))
    val allocator_vgpr_size_out = Wire(UInt(VGPR_ID_WIDTH.W))
    val allocator_sgpr_size_out = Wire(UInt(SGPR_ID_WIDTH.W))
    val allocator_lds_size_out = Wire(UInt(LDS_ID_WIDTH.W))
    val dis_controller_alloc_ack = Wire(Bool())
    val dis_controller_cu_busy = Wire(UInt(NUMBER_CU.W))
    val allocator_cu_valid = Wire(Bool())
    val allocator_cu_rejected = Wire(Bool())

    val allocator_neo_i = Module(new allocator_neo(WG_ID_WIDTH, CU_ID_WIDTH, NUMBER_CU, VGPR_ID_WIDTH, NUMBER_VGPR_SLOTS, SGPR_ID_WIDTH, NUMBER_SGPR_SLOTS, LDS_ID_WIDTH, NUMBER_LDS_SLOTS, NUMBER_WF_SLOTS, WF_COUNT_WIDTH, WG_SLOT_ID_WIDTH, WF_COUNT_WIDTH_PER_WG))
    val top_resource_table_i = Module(new top_resource_table(NUMBER_CU, CU_ID_WIDTH, RES_TABLE_ADDR_WIDTH, VGPR_ID_WIDTH + 1, NUMBER_VGPR_SLOTS, SGPR_ID_WIDTH + 1, NUMBER_SGPR_SLOTS, LDS_ID_WIDTH + 1, NUMBER_LDS_SLOTS, WG_ID_WIDTH, WF_COUNT_WIDTH, WG_SLOT_ID_WIDTH, NUMBER_WF_SLOTS, WF_COUNT_MAX, NUMBER_RES_TABLE, INIT_MAX_WG_COUNT, WF_COUNT_WIDTH_PER_WG))
    val inflight_wg_buffer_i = Module(new inflight_wg_buffer(WG_ID_WIDTH, WF_COUNT_WIDTH, CU_ID_WIDTH, VGPR_ID_WIDTH, SGPR_ID_WIDTH, LDS_ID_WIDTH, GDS_ID_WIDTH, ENTRY_ADDR_WIDTH, NUMBER_ENTRIES, WAVE_ITEM_WIDTH, MEM_ADDR_WIDTH, WF_COUNT_WIDTH_PER_WG))
    val gpu_interface_i = Module(new gpu_interface(WG_ID_WIDTH, WF_COUNT_WIDTH, WG_SLOT_ID_WIDTH, NUMBER_WF_SLOTS, NUMBER_CU, CU_ID_WIDTH, VGPR_ID_WIDTH, SGPR_ID_WIDTH, LDS_ID_WIDTH, TAG_WIDTH, MEM_ADDR_WIDTH, WAVE_ITEM_WIDTH, WF_COUNT_WIDTH_PER_WG))
    val dis_controller_i = Module(new dis_controller(NUMBER_CU, CU_ID_WIDTH, RES_TABLE_ADDR_WIDTH))
    allocator_cu_valid := allocator_neo_i.io.allocator_cu_valid
    allocator_cu_rejected := allocator_neo_i.io.allocator_cu_rejected
    allocator_wg_id_out := allocator_neo_i.io.allocator_wg_id_out
    allocator_cu_id_out := allocator_neo_i.io.allocator_cu_id_out
    allocator_wf_count := allocator_neo_i.io.allocator_wf_count
    allocator_vgpr_size_out := allocator_neo_i.io.allocator_vgpr_size_out
    allocator_sgpr_size_out := allocator_neo_i.io.allocator_sgpr_size_out
    allocator_lds_size_out := allocator_neo_i.io.allocator_lds_size_out
    allocator_vgpr_start_out := allocator_neo_i.io.allocator_vgpr_start_out
    allocator_sgpr_start_out := allocator_neo_i.io.allocator_sgpr_start_out
    allocator_lds_start_out := allocator_neo_i.io.allocator_lds_start_out
    allocator_neo_i.io.inflight_wg_buffer_alloc_wg_id := inflight_wg_buffer_alloc_wg_id
    allocator_neo_i.io.inflight_wg_buffer_alloc_num_wf := inflight_wg_buffer_alloc_num_wf
    allocator_neo_i.io.inflight_wg_buffer_alloc_vgpr_size := inflight_wg_buffer_alloc_vgpr_size
    allocator_neo_i.io.inflight_wg_buffer_alloc_sgpr_size := inflight_wg_buffer_alloc_sgpr_size
    allocator_neo_i.io.inflight_wg_buffer_alloc_lds_size := inflight_wg_buffer_alloc_lds_size
    allocator_neo_i.io.dis_controller_cu_busy := dis_controller_cu_busy
    allocator_neo_i.io.dis_controller_alloc_ack := dis_controller_alloc_ack
    allocator_neo_i.io.dis_controller_start_alloc := dis_controller_start_alloc
    allocator_neo_i.io.grt_cam_up_valid := grt_cam_up_valid
    allocator_neo_i.io.grt_cam_up_cu_id := grt_cam_up_cu_id
    allocator_neo_i.io.grt_cam_up_vgpr_strt := grt_cam_up_vgpr_strt
    allocator_neo_i.io.grt_cam_up_vgpr_size := grt_cam_up_vgpr_size
    allocator_neo_i.io.grt_cam_up_sgpr_strt := grt_cam_up_sgpr_strt
    allocator_neo_i.io.grt_cam_up_sgpr_size := grt_cam_up_sgpr_size
    allocator_neo_i.io.grt_cam_up_lds_strt := grt_cam_up_lds_strt
    allocator_neo_i.io.grt_cam_up_lds_size := grt_cam_up_lds_size
    allocator_neo_i.io.grt_cam_up_wf_count := grt_cam_up_wf_count
    allocator_neo_i.io.grt_cam_up_wg_count := grt_cam_up_wg_count
    inflight_wg_buffer_i.io.host_wg_valid := io.host_wg_valid
    inflight_wg_buffer_i.io.host_wg_id := io.host_wg_id
    inflight_wg_buffer_i.io.host_num_wf := io.host_num_wf
    inflight_wg_buffer_i.io.host_wf_size := io.host_wf_size
    inflight_wg_buffer_i.io.host_start_pc := io.host_start_pc
    inflight_wg_buffer_i.io.host_kernel_size_3d := io.host_kernel_size_3d
    inflight_wg_buffer_i.io.host_pds_baseaddr := io.host_pds_baseaddr
    inflight_wg_buffer_i.io.host_csr_knl := io.host_csr_knl
    inflight_wg_buffer_i.io.host_gds_baseaddr := io.host_gds_baseaddr
    inflight_wg_buffer_i.io.host_vgpr_size_total := io.host_vgpr_size_total
    inflight_wg_buffer_i.io.host_sgpr_size_total := io.host_sgpr_size_total
    inflight_wg_buffer_i.io.host_lds_size_total := io.host_lds_size_total
    inflight_wg_buffer_i.io.host_gds_size_total := io.host_gds_size_total
    inflight_wg_buffer_i.io.host_vgpr_size_per_wf := io.host_vgpr_size_per_wf
    inflight_wg_buffer_i.io.host_sgpr_size_per_wf := io.host_sgpr_size_per_wf
    inflight_wg_buffer_i.io.dis_controller_wg_alloc_valid := dis_controller_wg_alloc_valid
    inflight_wg_buffer_i.io.dis_controller_start_alloc := dis_controller_start_alloc
    inflight_wg_buffer_i.io.dis_controller_wg_dealloc_valid := dis_controller_wg_dealloc_valid
    inflight_wg_buffer_i.io.dis_controller_wg_rejected_valid := dis_controller_wg_rejected_valid
    inflight_wg_buffer_i.io.allocator_wg_id_out := allocator_wg_id_out
    inflight_wg_buffer_i.io.gpu_interface_dealloc_wg_id := gpu_interface_dealloc_wg_id
    io.inflight_wg_buffer_host_rcvd_ack := inflight_wg_buffer_i.io.inflight_wg_buffer_host_rcvd_ack
    io.inflight_wg_buffer_host_wf_done := inflight_wg_buffer_i.io.inflight_wg_buffer_host_wf_done
    io.inflight_wg_buffer_host_wf_done_wg_id := inflight_wg_buffer_i.io.inflight_wg_buffer_host_wf_done_wg_id
    inflight_wg_buffer_alloc_valid := inflight_wg_buffer_i.io.inflight_wg_buffer_alloc_valid
    inflight_wg_buffer_alloc_available := inflight_wg_buffer_i.io.inflight_wg_buffer_alloc_available
    inflight_wg_buffer_alloc_wg_id := inflight_wg_buffer_i.io.inflight_wg_buffer_alloc_wg_id
    inflight_wg_buffer_alloc_num_wf := inflight_wg_buffer_i.io.inflight_wg_buffer_alloc_num_wf
    inflight_wg_buffer_alloc_vgpr_size := inflight_wg_buffer_i.io.inflight_wg_buffer_alloc_vgpr_size
    inflight_wg_buffer_alloc_sgpr_size := inflight_wg_buffer_i.io.inflight_wg_buffer_alloc_sgpr_size
    inflight_wg_buffer_alloc_lds_size := inflight_wg_buffer_i.io.inflight_wg_buffer_alloc_lds_size
    inflight_wg_buffer_gpu_valid := inflight_wg_buffer_i.io.inflight_wg_buffer_gpu_valid
    inflight_wg_buffer_gpu_vgpr_size_per_wf := inflight_wg_buffer_i.io.inflight_wg_buffer_gpu_vgpr_size_per_wf
    inflight_wg_buffer_gpu_sgpr_size_per_wf := inflight_wg_buffer_i.io.inflight_wg_buffer_gpu_sgpr_size_per_wf
    inflight_wg_buffer_gpu_wf_size := inflight_wg_buffer_i.io.inflight_wg_buffer_gpu_wf_size
    inflight_wg_buffer_start_pc := inflight_wg_buffer_i.io.inflight_wg_buffer_start_pc
    inflight_wg_buffer_kernel_size_3d := inflight_wg_buffer_i.io.inflight_wg_buffer_kernel_size_3d
    inflight_wg_buffer_pds_baseaddr := inflight_wg_buffer_i.io.inflight_wg_buffer_pds_baseaddr
    inflight_wg_buffer_csr_knl := inflight_wg_buffer_i.io.inflight_wg_buffer_csr_knl
    inflight_wg_buffer_gds_base_dispatch := inflight_wg_buffer_i.io.host_gds_baseaddr
    gpu_interface_i.io.inflight_wg_buffer_gpu_valid := inflight_wg_buffer_gpu_valid
    gpu_interface_i.io.inflight_wg_buffer_gpu_wf_size := inflight_wg_buffer_gpu_wf_size
    gpu_interface_i.io.inflight_wg_buffer_start_pc := inflight_wg_buffer_start_pc
    gpu_interface_i.io.inflight_wg_buffer_kernel_size_3d := inflight_wg_buffer_kernel_size_3d
    gpu_interface_i.io.inflight_wg_buffer_pds_baseaddr := inflight_wg_buffer_pds_baseaddr
    gpu_interface_i.io.inflight_wg_buffer_csr_knl := inflight_wg_buffer_csr_knl
    gpu_interface_i.io.inflight_wg_buffer_gds_base_dispatch:=inflight_wg_buffer_gds_base_dispatch
    gpu_interface_i.io.inflight_wg_buffer_gpu_vgpr_size_per_wf := inflight_wg_buffer_gpu_vgpr_size_per_wf
    gpu_interface_i.io.inflight_wg_buffer_gpu_sgpr_size_per_wf := inflight_wg_buffer_gpu_sgpr_size_per_wf
    gpu_interface_i.io.allocator_wg_id_out := allocator_wg_id_out
    gpu_interface_i.io.allocator_cu_id_out := allocator_cu_id_out
    gpu_interface_i.io.allocator_wf_count := allocator_wf_count
    gpu_interface_i.io.allocator_vgpr_start_out := allocator_vgpr_start_out
    gpu_interface_i.io.allocator_sgpr_start_out := allocator_sgpr_start_out
    gpu_interface_i.io.allocator_lds_start_out := allocator_lds_start_out
    gpu_interface_i.io.dis_controller_wg_alloc_valid := dis_controller_wg_alloc_valid
    gpu_interface_i.io.dis_controller_wg_dealloc_valid := dis_controller_wg_dealloc_valid
    gpu_interface_alloc_available := gpu_interface_i.io.gpu_interface_alloc_available
    gpu_interface_dealloc_available := gpu_interface_i.io.gpu_interface_dealloc_available
    gpu_interface_cu_id := gpu_interface_i.io.gpu_interface_cu_id
    gpu_interface_dealloc_wg_id := gpu_interface_i.io.gpu_interface_dealloc_wg_id
    io.dispatch2cu_wf_dispatch := gpu_interface_i.io.dispatch2cu_wf_dispatch
    io.dispatch2cu_wg_wf_count := gpu_interface_i.io.dispatch2cu_wg_wf_count
    io.dispatch2cu_wf_size_dispatch := gpu_interface_i.io.dispatch2cu_wf_size_dispatch
    io.dispatch2cu_sgpr_base_dispatch := gpu_interface_i.io.dispatch2cu_sgpr_base_dispatch
    io.dispatch2cu_vgpr_base_dispatch := gpu_interface_i.io.dispatch2cu_vgpr_base_dispatch
    io.dispatch2cu_wf_tag_dispatch := gpu_interface_i.io.dispatch2cu_wf_tag_dispatch
    io.dispatch2cu_lds_base_dispatch := gpu_interface_i.io.dispatch2cu_lds_base_dispatch
    io.dispatch2cu_start_pc_dispatch := gpu_interface_i.io.dispatch2cu_start_pc_dispatch
    io.dispatch2cu_kernel_size_3d_dispatch := gpu_interface_i.io.dispatch2cu_kernel_size_3d_dispatch
    io.dispatch2cu_pds_baseaddr_dispatch := gpu_interface_i.io.dispatch2cu_pds_baseaddr_dispatch
    io.dispatch2cu_csr_knl_dispatch := gpu_interface_i.io.dispatch2cu_csr_knl_dispatch
    io.dispatch2cu_gds_base_dispatch := gpu_interface_i.io.dispatch2cu_gds_base_dispatch
    gpu_interface_i.io.cu2dispatch_wf_done := io.cu2dispatch_wf_done
    gpu_interface_i.io.cu2dispatch_wf_tag_done := io.cu2dispatch_wf_tag_done
    gpu_interface_i.io.cu2dispatch_ready_for_dispatch := io.cu2dispatch_ready_for_dispatch
    grt_cam_up_valid := top_resource_table_i.io.grt_cam_up_valid
    grt_cam_up_wf_count := top_resource_table_i.io.grt_cam_up_wf_count
    grt_cam_up_wg_count := top_resource_table_i.io.grt_cam_up_wg_count
    grt_cam_up_cu_id := top_resource_table_i.io.grt_cam_up_cu_id
    grt_cam_up_vgpr_strt := top_resource_table_i.io.grt_cam_up_vgpr_strt
    grt_cam_up_vgpr_size := top_resource_table_i.io.grt_cam_up_vgpr_size
    grt_cam_up_sgpr_strt := top_resource_table_i.io.grt_cam_up_sgpr_strt
    grt_cam_up_sgpr_size := top_resource_table_i.io.grt_cam_up_sgpr_size
    grt_cam_up_lds_strt := top_resource_table_i.io.grt_cam_up_lds_strt
    grt_cam_up_lds_size := top_resource_table_i.io.grt_cam_up_lds_size
    grt_wg_alloc_done := top_resource_table_i.io.grt_wg_alloc_done
    grt_wg_alloc_wg_id := top_resource_table_i.io.grt_wg_alloc_wg_id
    grt_wg_alloc_cu_id := top_resource_table_i.io.grt_wg_alloc_cu_id
    grt_wg_dealloc_done := top_resource_table_i.io.grt_wg_dealloc_done
    grt_wg_dealloc_wg_id := top_resource_table_i.io.grt_wg_dealloc_wg_id
    grt_wg_dealloc_cu_id := top_resource_table_i.io.grt_wg_dealloc_cu_id
    top_resource_table_i.io.gpu_interface_cu_id := gpu_interface_cu_id
    top_resource_table_i.io.gpu_interface_dealloc_wg_id := gpu_interface_dealloc_wg_id
    top_resource_table_i.io.dis_controller_wg_alloc_valid := dis_controller_wg_alloc_valid
    top_resource_table_i.io.dis_controller_wg_dealloc_valid := dis_controller_wg_dealloc_valid
    top_resource_table_i.io.allocator_wg_id_out := allocator_wg_id_out
    top_resource_table_i.io.allocator_wf_count := allocator_wf_count
    top_resource_table_i.io.allocator_cu_id_out := allocator_cu_id_out
    top_resource_table_i.io.allocator_vgpr_start_out := allocator_vgpr_start_out
    top_resource_table_i.io.allocator_vgpr_size_out := allocator_vgpr_size_out
    top_resource_table_i.io.allocator_sgpr_start_out := allocator_sgpr_start_out
    top_resource_table_i.io.allocator_sgpr_size_out := allocator_sgpr_size_out
    top_resource_table_i.io.allocator_lds_start_out := allocator_lds_start_out
    top_resource_table_i.io.allocator_lds_size_out := allocator_lds_size_out
    dis_controller_start_alloc := dis_controller_i.io.dis_controller_start_alloc
    dis_controller_alloc_ack := dis_controller_i.io.dis_controller_alloc_ack
    dis_controller_wg_alloc_valid := dis_controller_i.io.dis_controller_wg_alloc_valid
    dis_controller_wg_dealloc_valid := dis_controller_i.io.dis_controller_wg_dealloc_valid
    dis_controller_wg_rejected_valid := dis_controller_i.io.dis_controller_wg_rejected_valid
    dis_controller_cu_busy := dis_controller_i.io.dis_controller_cu_busy
    dis_controller_i.io.inflight_wg_buffer_alloc_valid := inflight_wg_buffer_alloc_valid
    dis_controller_i.io.inflight_wg_buffer_alloc_available := inflight_wg_buffer_alloc_available
    dis_controller_i.io.allocator_cu_valid := allocator_cu_valid
    dis_controller_i.io.allocator_cu_rejected := allocator_cu_rejected
    dis_controller_i.io.allocator_cu_id_out := allocator_cu_id_out
    dis_controller_i.io.grt_wg_alloc_done := grt_wg_alloc_done
    dis_controller_i.io.grt_wg_dealloc_done := grt_wg_dealloc_done
    dis_controller_i.io.grt_wg_alloc_cu_id := grt_wg_alloc_cu_id
    dis_controller_i.io.grt_wg_dealloc_cu_id := grt_wg_dealloc_cu_id
    dis_controller_i.io.gpu_interface_alloc_available := gpu_interface_alloc_available
    dis_controller_i.io.gpu_interface_dealloc_available := gpu_interface_dealloc_available
    dis_controller_i.io.gpu_interface_cu_id := gpu_interface_cu_id
}